1. Field of the Invention
The present invention relates to a semiconductor device provided with an analogue element part and a digital element part formed as a pair of insulated gate transistors on the same semiconductor substrate, and to a method for fabricating the semiconductor device.
2. Description of the Prior Art
Conventionally, insulated gate transistor technology (hereinafter, MOS technology), and, in particular, the complementary-type insulated gate transistor technology (hereinafter, CMOS technology) and the N-channel type insulated gate transistor (NMOS transistor) technology are the main types of technology for fabricating silicon devices at the present time. In these technologies, the development of miniaturization, together with a high degree of integration and conversion to high speed, have shown steady progress and these features are being widely adopted for all types of equipment. The development of these technologies has been mainly in the application to digital circuits and the digital operation of digital ICs and the like. Along with the advancement of miniaturization, the conversion to low voltage power sources has also been implemented for use in these circuits.
In addition, taking full advantage of the low power consumption, which is one of the features of CMOS, the fabrication of parts such as analogue circuits, analogue ICs, and the like which perform an analogue operation, has made considerable progress using MOS technology, and the use of these parts in finished products is rapidly expanding.
Accordingly, an example of a single semiconductor device in which an analogue element part and a digital element part formed by CMOS on the same chip will now be explained with reference to the drawings.
FIG. 1 is a sectional view of this semiconductor device. An N-channel type MOS transistor 2 and a P-channel type MOS transistor 3 of an analogue element part 1 are formed on the right side of the drawing, and an N-channel type MOS transistor 5 and a P-channel type MOS transistor 6 of a digital element part 4 are formed on the left side of the drawing.
Also shown on the drawing are a P-type silicon substrate 7; a plurality of N-well diffusion layers 8 provided in the silicon substrate 7; a plurality of field-oxidized films 9 provided at each separation on the silicon substrate 7; a plurality of P.sup.- reversal prevention layers 10 formed along the field-oxidized films 9; a plurality of N+ diffusion layers 11 formed on the silicon substrate 7 between the field-oxidized films 9; a plurality of P+ diffusion layers 12 formed on the N-well diffusion layers 8 between the field-oxidized films 9; a plurality of boron-phosphorus silicate glass films 13 (hereinafter BPSG film) formed on each of the diffusion layers 11, 12 and the silicon substrate 7, and also on the field-oxidized films 9; a plurality of N+ polysilicon films 14 which are provided to form a gate in each of the BPSG films 13 on the silicon substrate 7; and aluminum wiring 15 in a plurality of positions.
When the analogue element part 1 and the digital element part 4 are formed by CMOS technology on the same chip in this manner, the analogue element part 1 is provided on the peripheral part of the chip, and the dense digital element part 4 is provided at the core section of the chip.
Aiming at high speed and high integration in the digital element part 4, miniaturization including a gate oxidized film is proceeding rapidly, and large-scale digital circuits containing from several thousands to over ten thousand gates are not being fabricated.
In order to fabricate a miniaturized, normal digital element part 4, the analogue element part 1 is formed before the digital element part 4. In addition, when it is desired to fabricate an analogue element part 1 such as an analogue circuit or analogue IC using CMOS technology, for example, when an inverter operation is considered, a linear (analogue) region on a characteristic curve capable of being activated is small. For this reason, when a low voltage power source (for example V.sub.HH =5 V) is adopted as a power source, a large operating margin is considered impossible to obtain.
Accordingly, the gate oxidized film must be thick, the surface density must be reduced, and, in addition, a high voltage power source of 9 to 10 V must be adopted. Further, to form the digital element part 4 after the analogue element part 1 is formed, various types of treatment such as oxidized film etching and heat treatment and the like are required during the forming of the digital element part 4 and this results in electrically weak parts A being produced. For this reason, leak current is increased, or the gate tolerance to pressure is reduced, or the like, so that there is little margin with respect to both yield and reliability, which is a drawback.